In order to highly integrate a semiconductor device and to obtain high performance of the semiconductor device, a metal line having a multi-layer structure has been widely used. Although aluminum (Al) is widely used for the metal line, recently, copper (Cu) having superior conductivity has been substituted for aluminum (Al).
However, since a copper line layer is not easily patterned, the copper line layer is mainly formed through a damascene process and a chemical mechanical polishing (CMP) process.
FIGS. 1A to 1B are cross-sectional views showing a method for manufacturing a related semiconductor device.
Referring to FIG. 1A, an interlayer dielectric layer 110 is formed on a semiconductor substrate 100. A via hole 113 is formed in the interlayer dielectric layer 110 through a damascene process.
A barrier layer 120 is formed on the interlayer dielectric layer 110 including the via hole 113 to block the diffusion of copper (Cu).
A seed layer 130 is formed on the barrier layer 120 to enable copper (Cu) to be easily deposited. The seed layer 130 may be formed through a physical vapor deposition (PVD) process.
When the seed layer 130 is formed through the PVD process, the seed layer 130 becomes relatively thicker at an inlet of the via hole 113, that is, at a corner area 133 of an upper portion of the via hole 113, so that an overhang may be formed. Accordingly, the seed layer 130 is not easily formed on the barrier layer 120 at the side surface of the via hole 113 due to the overhang. Accordingly, an area in which the seed layer 130 is not formed on the barrier layer 120 at the side surface of the via hole 113, that is, a discontinuous step coverage area 136 exists.
Since the seed layer 130 does not exist in the discontinuous step coverage area 136, the copper material may not be easily deposited in the discontinuous step coverage area 136 when the copper material is buried in the following process.
Referring to FIG. 1B, a copper layer 140 is formed on the seed layer 130 including the via hole 113.
In this case, although the copper layer 140 is not sufficiently formed at the side surface of the via hole 113 due to the overhang, the copper layer 140 is easily formed on the bottom surface of the via hole 113. Accordingly, a void 143 or a long seam may be created in the copper layer 140 of the via hole 113.
Meanwhile, recently, as the line width of a metal line is reduced, the barrier layer 120 and the seed layer 130 gradually become thinner.
However, as the barrier layer 120 becomes thinner, the performance of the barrier layer may be degraded.
In addition, as the seed layer 130 becomes thinner, the discontinuous step coverage frequently occurs, so that the probability of creating the void is increased.
Thus, there exists a need in the art for an improved metal line for a semiconductor device.